Caple C702G Manual de servicio Pagina 130
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8-5
3) Video Bias Circuit
The video signal is amplified maximum 45Vpp in IC721 output, then the signal is done DC bias by video bias
circuit through C729G. This DC voltage varies when cut off adjustment and brightness adjustment.
The video bias circuit consists of fixed voltage circuit construction with op-amp. Q741G is used high-voltage
transistor due to get approx.80V to 170V at cathode black level voltage.
The voltage from DAC IC751 input
(Fig 1.3) Brightness and Cut-off Control
4) ABL Circuit
The ABL circuit consists of the part (Q771,Q772 and peripherals) which detects and amplifies the current
flowing to the CRT anode, and the other parts (IC711) which control the gain of the video signal (R,G and B).
The ABL circuit limits the amplitude of the video signal and serves to keep the maximum average current
flowing to the CRT up to 750
μ
A. When the anode current is less than 750
μ
A, Q772 does not operate. And
the anode current attempts to exceed 750μA, Q772 operates and the voltage of IC711 pin 15 drops, the
gain of IC711 drops. After saturation of IC711 pin 15, D713 becomes ON, then IC711 pin 30 drops. This is
the voltage that decides the black level of IC711 video output. Therefore back raster becomes dark.
(Fig 1.4) ABL Circuit
Cathod
R74GG
IC801
CPU
C729G
R742G
D741G
I
2
C BUS
-
+
+12V
C744G
R747G
R748G
Q741G
R749G
Auto Adjust
R74AG
R744G R743G
R746G
+
12V
IC751
M62393FP
15
5
14
G_BRT
G_BIAS
SUB_BIAS
C743GR745G
R741G
+22
0
V
IC721
14
R74FG
R74EG
C741G
TP-G
CRT
BLANKING
C7E4
G1
R904 R903
C902 C901
L901G
R901G
R902G
SG901G
SG902
HIGH VOLTAGE
R5U3
R5U2
R5U1
+
80V
T5R1
F.B .T
8
+
15V
IC711
M52742ASP
VIDEO
PRE AMP
15
30
23
ABL IN
GAIN
MAIN
BRIGHT
-NESS
+12V
+12V
C5F2
ZD5F1
Q5F2
R771
D771C771
R772
R773
R774
Q772
Q771
R775
D713
R713
R714
D712
D711
SW/HV PWB
VIDEO PWB
- SERVICE MANUAL 1
- PRODUCT SAFETY CAUTION 3
- CONTENTS 4
- SPECIFICATIONS 5
- CONTROLS 6
- SERIAL NUMBER INFORMATION 9
- ASSEMBLY 10
- Mount the EMF PWB 13
- Clamp the connector 13
- Insert a pencil between PLATE 21
- SHIELDING CRT ASSY and CN-CL 21
- CN-LEB as per sketch 21
- Clamp CN-CA, CN-CC 23
- ADJUSTMENT PROCEDURES 30
- Magnetized Pattern Example 32
- MultiSync 33
- OSD MENU (S) 36
- OSD MENU (U) 38
- ADJUSTMENT ITEMS 40
- [A] Pre-Adjustment 41
- [B] Initial Settings 41
- [C] Main Adjustment 41
- Center line 50
- XLeft XRight 52
- 45 +0/-1 55
- Vertical Cycle 59
- [D] Reference 65
- 16 VESA 1280*1024@60H 69
- 21 VESA 1280*1024@75Hz 70
- VESA 1920*1440@75Hz 70
- 25 H.HOLD1 70
- 640*480@140Hz 72
- 1280*1024@70Hz 73
- 1024*768@100Hz 73
- 800*600@120Hz 73
- 640*480@160Hz 73
- 800*600@140Hz 73
- Fig.3-1 SW/HV PWB 76
- Fig.3-2 CONT PWB 76
- Fig.3-3 SW PWB 76
- Fig.3-9 DEF PWB 79
- Fig.3-10 OSC PWB 79
- Program Disk 81
- TROUBLE SHOOTING 89
- 1. NO RASTER 90
- 3. UNSTABLE 96
- 5. ABNORMAL PICTURE 99
- 110
- 8. SELF TEST ERROR 112
- 10. RASTER ROTATION ERROR 113
- 14. MOIRE CANCEL FAILURE 121
- 15. PLUG & PLAY FAILURE 122
- 16. OUT OF Cg-SPECIFICATION 123
- 17. USB CIRCUIT FAILURE 124
- CIRCUIT DESCRIPTION 126
- 1. VIDEO CIRCIT 128
- SUB_BIAS 130
- BLANKING 130
- 2. DEFLECTION CIRCUIT 132
- Q571 H.LINEARITY2 136
- H.LINEARITY1 136
- Horizontal Frequency 136
- H.Out Trans 138
- +B Modulator 138
- PWM Chopper 138
- V SAW Input 141
- 3. HIGH VOLTAGE CIRCUIT 142
- 4. BLANKING CIRCUIT 144
- 5. DYNAMIC FOCUS CIRCUIT 145
- 6. CPU CIRCUIT 147
- BNC/D-SUB 152
- 22pin voltage 166
- BOTTOM LEFT 186
- BOTTOM RIGHT 186
- 11. USB CIRCUIT 187
- 12. AUTO ADJUST CIRCUIT 188
- REPLACEMENT PARTS LIST 189
- MAIN CPU 265
- for Human Potential 266
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