Caple C871i Manual de usuario descargar pdf (Pagina 480)

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Apple II Computer Info

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### FILE : ssc.regs

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### Created : Sunday, January 14, 1996 Modified: Sunday, January 14, 1996

### File Type: "TEXT" File Creator: "LMAN"

### File Size: 8558 bytes 8 KB

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Path: news.weeg.uiowa.edu!news.uiowa.edu!hobbes.physics.uiowa.edu!math.ohio-

state.edu!howland.reston.ans.net!usc!news.service.uci.edu!cerritos.edu!wilbur!qed!

quor

Newsgroups: comp.sys.apple2.programmer

Subject: Re: SSC info wanted (again)

Message-ID: <[email protected]>

From: [email protected] (Matthew Ghio)

Date: 20 Jul 93 06:37:51 GMT

Sender: [email protected]

References: <199307152147.AA18084@ghostwheel./jointfilesconvert/483152/bga.com>

Organization: The QED BBS, Lakewood CA

Lines: 96

khym@ghostwheel./jointfilesconvert/483152/bga.com (Dave Huang) writes:

> OK, try #3.. if this doesn't work I'll have to steal someone's NNTP

> server :-) (and apologies if you've seen this before :)

> I was wondering, what do $C088 + n0 through $C08B + n0 on a Super

> Serial Card do?

Ok, here's something I dug up from my archives (you're not the first person to ask

that question)...

-------------------------------------------------------------------------------

Programming the Apple Super Serial Card and compatible serial interfaces:

These docs brought to you by Quor, March 27, 1993.

The SSC has four registers beginning at $C088 plus the slot number of the SSC

multiplied by 16. They are described below:

$C0x8: Send/receive register

When a byte is received, it is placed in this register, and can be read. Writing

a byte to this register sends it out.

$C0x9: Status Register (read only)

bit 0: This is set when a parity error has been detected.

bit 1: This is set when a framing error has been detected.

bit 2: This is set when an overrun occured (data was not read and has been

lost)

bit 3: This is set when a new byte has been received and is waiting in the

receive register.

bit 4: This is set when the transmit register is empty, and therefore is ready

to send another byte.

bit 5: This reports the status of the data carrier detect (DCD)

bit 6: This reports the status of the data set ready (DSR)

Apple II Computer Technical Information : Apple II Family Hardware Info

ftp://ground.ecn.uiowa.edu/2/apple2/miscinfo/hardware : May 2001 : 480 of 572

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Caple C871i Manual de usuario Pagina 480

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Caple C871i Manual de usuario Pagina 480

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