Caple C871i Manual de usuario descargar pdf (Pagina 489)

100

101

Apple II Computer Info

32 - transmitter controls (RTS signal)

0 0 = transmit IRQ disabled, RTS high

0 1 = transmit IRQ enabled, RTS low

1 0 = transmit IRQ disabled, RTS low

1 1 = transmit IRQ disabled, RTS low, send break

1 - receive IRQ enable

0 = enabled

1 = disabled

0 - data terminal ready

0 = disable receiver/transmitter (DTR high)

1 = enable receiver/transmitter (DTR low)

STATREG ($C089 + $n0) (read/write -- write causes master reset)

7 - IRQ pending status

0 = no interrupt

1 = interrupt has occurred

6 - data ready (DSR)

0 = DSR low (ready)

1 = DSR high (not ready)

5 - carrier detect (DCD)

0 = DCD low (detected)

1 = DCD high (not detected)

4 - transmission register empty

0 = not empty

1 = empty

3 - receipt register full

0 = not full

1 = full

2 - overrun error (two receives since last IRQ servicing)

0 = no overrun

1 = overrun

1 - framing error (word length mismatch)

0 = no framing error

1 = framing error detected

0 - parity error (NOTE: mark and space parity are not checked)

0 = no parity error

1 = parity error detected

RDREG ($C088 + $n0) (read only)

TDREG ($C088 + $n0) (write only)

The addresses are the base mapping to the I/O registers on an Apple II

added to the slot in which the card resides multiplied by sixteen.

| Kevin Scott

| [email protected]

Sean Dockery | Tickle us, do we not laugh?

Griffin Software Development Group | Prick us, do we not bleed?

[email protected] | Wrong us, shall we not revenge?

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Apple II Computer Technical Information : Apple II Family Hardware Info

ftp://ground.ecn.uiowa.edu/2/apple2/miscinfo/hardware : May 2001 : 489 of 572

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Caple C871i Manual de usuario Pagina 489

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Caple C871i Manual de usuario Pagina 489

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